模拟设计工程师（工作地点可选合肥/上海）

Position Description:

Responsible for the design and development of analog mixed signal Serdes/AFE/High-speed IO macros from initial concept/specification to final verification and match the design requirements. Candidates should have experience on high speed Serdes designs and have good knowledge on common Serdes standards or AFE or high speed IO including electrical requirements. Candidates must have deep design experience in one of the following Serdes blocks: Driver; ADC/DAC; Receiver; Serializer; Deserializer; Phase Interpolator; Low Jitter PLL; High Speed Clock Distribution.

Position Requirement:

Must have BS degree with 7+ years of applicable experience, MS degree with 5+ years of applicable experience in microelectronics, electrical engineering. Candidate must be able to own a block or set of blocks for analog SerDes/AFE/high speed IO IC design. Candidate needs to be familiar with the design process, required handoffs to the top-level design team for smooth integration, and robust block verification. Proficiency in using EDA tools for circuit simulation, layout and physical verification with the design experience at more than 6.25Gbps and in <40nm technologies are preferred.

职位描述：               
负责设计和开发的模拟/混合信号电路的AFE /高速IO宏从初始概念/最终检验规范和两个匹配的设计要求。有经验的候选人应该在高速电路设计和有良好的知识在普通的SerDes标准或安全或高速IO包括电器的要求。候选人必须有深的设计经验，在下面的一块电路：驱动；ADC / DAC；接收机；序列化程序序列化器的相位内插器；低；跳动；锁相环；高速时钟分配。
职位要求：              
必须具有学士学位，7年以上相关工作经验，硕士学位，5年以上微电子、电气工程相关工作经验。候选人必须能够拥有模拟SERDES/AFE/高速IO IC设计的一个或一组模块。候选人需要熟悉设计过程，需要移交给顶层设计团队，以便顺利集成，以及强大的块验证。熟练使用EDA工具进行电路模拟、布局和物理验证，具有6.25Gbps以上和40nm以下技术的设计经验者优先。